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| PRELIMINARY FEMTOCLOCKSTM CRYSTAL-TOLVHSTL FREQUENCY SYNTHESIZER ICS8422002I-01 Features * * * * * * * * Two LVHSTL outputs (VOHmax = 1.2V) Selectable crystal oscillator interface or LVCMOS/LVTTL single-ended input Supports the following output frequencies: 156.25MHz, 125MHz, 62.5MHz VCO range: 560MHz - 680MHz RMS phase jitter @ 156.25MHz, using a 25MHz crystal (1.875MHz - 20MHz): 0.44ps (typical) Power supply modes: Core/Output 3.3V/1.8V 2.5V/1.8V -40C to 85C ambient operating temperature Available in both standard (RoHS 5) and lead-free (RoHS 6) packages General Description The ICS8422002I-01 is a 2 output LVHSTL Synthesizer optimized to generate Ethernet HiPerClockSTM reference clock frequencies and is a member of the HiPerClocksTM family of high performance clock solutions from IDT. Using a 25MHz 18pF parallel resonant crystal, the following frequencies can be generated based on the 2 frequency select pins (F_SEL[1:0]): 156.25MHz, 125MHz and 62.5MHz. The ICS8422002I-01 uses IDT's 3rd generation low phase noise VCO technology and can achieve 1ps or lower typical rms phase jitter, easily meeting Ethernet jitter requirements. The ICS8422002I-01 is packaged in a small 20-pin TSSOP package. ICS Pin Assignment nc VDDO Q0 nQ0 MR nPLL_SEL nc VDDA F_SEL0 VDD 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 VDDO Q1 nQ1 GND VDD nXTAL_SEL REF_CLK XTAL_IN XTAL_OUT F_SEL1 Block Diagram F_SEL[1:0] Pulldown nPLL_SEL Pulldown 2 ICS422002I-01 20-Lead TSSOP 6.5mm x 4.4mm x 0.925mm package body G Package Top View Q0 1 F_SEL[1:0] 0 0 /4 0 1 /5 1 0 /10 1 1 Not Used nQ0 REF_CLK Pulldown 25MHz 1 XTAL_IN OSC XTAL_OUT nXTAL_SEL Pulldown 0 Phase Detector VCO Q1 nQ1 0 M = 25 (fixed) MR Pulldown The Preliminary Information presented herein represents a product in pre-production. The noted characteristics are based on initial product characterization and/or qualification. Integrated Device Technology, Incorporated (IDT) reserves the right to change any circuitry or specifications without notice. IDTTM / ICSTM LVHSTL FREQUENCY SYNTHESIZER 1 ICS8422002AGI-01 REV. C NOVEMBER 1, 2007 ICS8422002I-01 FEMTOCLOCKSTM CRYSTAL-TO-LVHSTL FREQUENCY SYNTHESIZER PRELIMINARY Table 1. Pin Descriptions Number 1, 7 2, 20 3, 4 Name nc VDDO Q0, nQ0 Power Output Type Unused Description No connect. Output supply pins. Differential output pair. LVHSTL interface levels. Active HIGH Master Reset. When logic HIGH, the internal dividers are reset causing the true outputs Qx to go low and the inverted outputs nQx to go high. When logic LOW, the internal dividers and the outputs are enabled. LVCMOS/LVTTL interface levels. Selects between the PLL and REF_CLK as input to the dividers. When LOW, selects PLL (PLL Enable). When HIGH, deselects the reference clock (PLL Bypass). LVCMOS/LVTTL interface levels. Analog supply pin. Pulldown Frequency select pins. LVCMOS/LVTTL interface levels. Core supply pins. Parallel resonant crystal interface. XTAL_OUT is the output, XTAL_IN is the input. Pulldown Pulldown Single-ended reference clock input. LVCMOS/LVTTL interface levels. Selects between crystal or REF_CLK inputs as the PLL Reference source. Selects XTAL inputs when LOW. Selects REF_CLK when HIGH. LVCMOS/LVTTL interface levels. Power supply ground. Differential output pair. LVHSTL interface levels. 5 MR Input Pulldown 6 8 9, 11 10, 16 12, 13 14 15 17 18, 19 nPLL_SEL VDDA F_SEL0, F_SEL1 VDD XTAL_OUT, XTAL_IN REF_CLK nXTAL_SEL GND nQ1, Q1 Input Power Input Power Input Input Input Power Output Pulldown NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. Table 2. Pin Characteristics Symbol CIN RPULLDOWN Parameter Input Capacitance Input Pulldown Resistor Test Conditions Minimum Typical 4 51 Maximum Units pF k IDTTM / ICSTM LVHSTL FREQUENCY SYNTHESIZER 2 ICS8422002AGI-01 REV. C NOVEMBER 1, 2007 ICS8422002I-01 FEMTOCLOCKSTM CRYSTAL-TO-LVHSTL FREQUENCY SYNTHESIZER PRELIMINARY Absolute Maximum Ratings NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. Item Supply Voltage, VDD Inputs, VI Outputs, IO Continuous Current Surge Current Package Thermal Impedance, JA Storage Temperature, TSTG Rating 4.6V -0.5V to VDD + 0.5V 50mA 100mA 73.2C/W (0 lfpm) -65C to 150C DC Electrical Characteristics Table 3A. Power Supply DC Characteristics, VDD = VDDA = 3.3V 5%, VDDO = 1.8V 0.2V, TA = -40C to 85C Symbol VDD VDDA VDDO IDD IDDA IDDO Parameter Core Supply Voltage Analog Supply Voltage Output Supply Voltage Core Supply Current Analog Supply Current Output Supply Current Test Conditions Minimum 3.135 3.135 1.6 Typical 3.3 3.3 1.8 90 10 0 Maximum 3.465 3.465 2.0 Units V V V mA mA mA Table 3B. Power Supply DC Characteristics, VDD = VDDA = 2.5V 5%, VDDO = 1.8V 0.2V, TA = -40C to 85C Symbol VDD VDDA VDDO IDD IDDA IDDO Parameter Core Supply Voltage Analog Supply Voltage Output Supply Voltage Core Supply Current Analog Supply Current Output Supply Current Test Conditions Minimum 2.375 2.375 1.6 Typical 2.5 2.5 1.8 80 10 0 Maximum 2.625 2.625 2.0 Units V V V mA mA mA IDTTM / ICSTM LVHSTL FREQUENCY SYNTHESIZER 3 ICS8422002AGI-01 REV. C NOVEMBER 1, 2007 ICS8422002I-01 FEMTOCLOCKSTM CRYSTAL-TO-LVHSTL FREQUENCY SYNTHESIZER PRELIMINARY Table 3C. LVCMOS/LVTTL DC Characteristics, TA = -40C to 85C Symbol VIH Parameter Input High Voltage Test Conditions VDD = 3.3V VDD = 2.5V Input Low Voltage Input High Current Input Low Current REF_CLK, MR, F_SEL[0:1], nPLL_SEL, nXTAL_SEL REF_CLK, MR, F_SEL[0:1], nPLL_SEL, nXTAL_SEL VDD = 3.3V VDD = 2.5V VDD = VIN = 3.465V or 2.625V VDD = 3.465V or 2.625V, VIN = 0V -5 Minimum 2 1.7 -0.3 -0.3 Typical Maximum VDD + 0.3 VDD + 0.3 0.8 0.7 150 Units V V V V A A VIL IIH IIL Table 3D. LVHSTL DC Characteristics, VDD = VDDA = 3.3V 5%, VDDO = 1.8V 0.2V, TA = -40C to 85C Symbol VOH VOL VOX VSWING Parameter Output High Current; NOTE 1 Output Low Current; NOTE 1 Output Crossover Voltage; NOTE 2 Peak-to-Peak Output Voltage Swing Test Conditions Minimum 1.0 0 40 0.6 Typical Maximum 1.2 0.4 60 1.1 Units V V % V NOTE 1: Outputs termination with 50 to ground. NOTE 2: Defined with respect to output voltage swing at a given condition. Table 3E. LVHSTL DC Characteristics, VDD = VDDA = 2.5V 5%, VDDO = 1.8V 0.2V, TA = -40C to 85C Symbol VOH VOL VOX VSWING Parameter Output High Current; NOTE 1 Output Low Current; NOTE 1 Output Crossover Voltage; NOTE 2 Peak-to-Peak Output Voltage Swing 40 0.9 Test Conditions Minimum 1.0 0.235 60 Typical Maximum 1.2 Units V V % V NOTE 1: Outputs termination with 50 to ground. NOTE 2: Defined with respect to output voltage swing at a given condition. Table 4. Crystal Characteristics Parameter Mode of Oscillation Frequency Equivalent Series Resistance (ESR) Shunt Capacitance Drive Level 22.4 Test Conditions Minimum Typical Fundamental 25 27.2 50 7 1 MHz Maximum Units pF mW IDTTM / ICSTM LVHSTL FREQUENCY SYNTHESIZER 4 ICS8422002AGI-01 REV. C NOVEMBER 1, 2007 ICS8422002I-01 FEMTOCLOCKSTM CRYSTAL-TO-LVHSTL FREQUENCY SYNTHESIZER PRELIMINARY AC Electrical Characteristics Table 5A. AC Characteristics, VDD = VDDA = 3.3V 5%, VDDO = 1.8V 0.2V, TA = -40C to 85C Parameter fOUT tsk(o) tjit() tR / tF odc Symbol Output Frequency Output Skew; NOTE 1, 2 156.25MHz, (1.875MHz - 20MHz) RMS Phase Jitter (Random); NOTE 3 Output Rise/Fall Time Output Duty Cycle 125MHz, (1.875MHz - 20MHz) 62.5MHz, (1.875MHz - 20MHz) 20% to 80% Test Conditions F_SEL[1:0] = 00 F_SEL[1:0] = 01 F_SEL[1:0] = 10 Minimum 140 112 56 TBD 0.44 0.48 0.49 410 50 Typical Maximum 170 136 68 Units MHz MHz MHz ps ps ps ps ps % NOTE 1: Defined as skew between outputs at the same supply voltages and with equal load conditions. Measured at VDDO/2. NOTE 2: This parameter is defined in accordance with JEDEC Standard 65. NOTE 3: Please refer to the Phase Noise Plot. Table 5B. AC Characteristics, VDD = VDDA = 2.5V 5%, VDDO = 1.8V 0.2V, TA = -40C to 85C Parameter fOUT tsk(o) tjit() tR / tF odc Symbol Output Frequency Output Skew; NOTE 1, 2 156.25MHz, (1.875MHz - 20MHz) RMS Phase Jitter (Random); NOTE 3 Output Rise/Fall Time Output Duty Cycle 125MHz, (1.875MHz - 20MHz) 62.5MHz, (1.875MHz - 20MHz) 20% to 80% Test Conditions F_SEL[1:0] = 00 F_SEL[1:0] = 01 F_SEL[1:0] = 10 Minimum 140 112 56 TBD 0.41 0.49 0.50 380 50 Typical Maximum 170 136 68 Units MHz MHz MHz ps ps ps ps ps % NOTE 1: Defined as skew between outputs at the same supply voltages and with equal load conditions. Measured at VDDO/2. NOTE 2: This parameter is defined in accordance with JEDEC Standard 65. NOTE 3: Please refer to the Phase Noise Plot. IDTTM / ICSTM LVHSTL FREQUENCY SYNTHESIZER 5 ICS8422002AGI-01 REV. C NOVEMBER 1, 2007 ICS8422002I-01 FEMTOCLOCKSTM CRYSTAL-TO-LVHSTL FREQUENCY SYNTHESIZER PRELIMINARY Typical Phase Noise at 156.25MHz -10 -20 -30 -40 -50 dBc Hz -60 -70 -80 -90 -100 -110 -120 -130 -140 -160 -170 -180 -190 100 -150 156.25MHz RMS Phase Jitter (Random) 1.875MHz to 20MHz = 0.44ps (typical) Ethernet Filter 100k 0 Noise Power 1k 10k Offset Frequency (Hz) Raw Phase Noise Data Phase Noise Result by adding an Ethernet filter to raw data 1M 10M 100M IDTTM / ICSTM LVHSTL FREQUENCY SYNTHESIZER 6 ICS8422002AGI-01 REV. C NOVEMBER 1, 2007 ICS8422002I-01 FEMTOCLOCKSTM CRYSTAL-TO-LVHSTL FREQUENCY SYNTHESIZER PRELIMINARY Parameter Measurement Information 3.3V5% 1.8V0.2V 2.5V5% 1.8V0.2V VDD, VDDA VDDO Qx SCOPE VDD, VDDA VDDO Qx SCOPE LVHSTL GND nQx LVHSTL GND nQx 0V 0V 3.3V/1.8V Output Load AC Test Circuit 2.5V/1.8V Output Load AC Test Circuit Phase Noise Plot Noise Power nQx Qx Phase Noise Mask nQy Qy tsk(o) f1 Offset Frequency f2 RMS Jitter = Area Under the Masked Phase Noise Plot Output Skew RMS Phase Jitter nQ0, nQ1 Q0, Q1 80% Clock Outputs 80% VSW I N G t PW t PERIOD 20% tR tF 20% odc = t PW t PERIOD x 100% Output Rise/Fall Time Output Duty Cycle/Pulse Width/Period IDTTM / ICSTM LVHSTL FREQUENCY SYNTHESIZER 7 ICS8422002AGI-01 REV. C NOVEMBER 1, 2007 ICS8422002I-01 FEMTOCLOCKSTM CRYSTAL-TO-LVHSTL FREQUENCY SYNTHESIZER PRELIMINARY Application Information Power Supply Filtering Technique As in any high speed analog circuitry, the power supply pins are vulnerable to random noise. To achieve optimum jitter performance, power supply isolation is required. The ICS8422002I-01 provides separate power supplies to isolate any high switching noise from the outputs to the internal PLL. VDD, VDDA and VDDO should be individually connected to the power supply plane through vias, and 0.01F bypass capacitors should be used for each pin. Figure 1 illustrates this for a generic VDD pin and also shows that VDDA requires that an additional 10 resistor along with a 10F bypass capacitor be connected to the VDDA pin. 3.3V VDD .01F VDDA .01F 10F 10 Figure 1. Power Supply Filtering Recommendations for Unused Input and Output Pins Inputs: LVCMOS Control Pins All control pins have internal pull-ups or pull-downs; additional resistance is not required but can be added for additional protection. A 1k resistor can be used. Outputs: LVHSTL Outputs All unused LVHSTL outputs can be left floating. We recommend that there is no trace attached. Both sides of the differential output pair should either be left floating or terminated. Crystal INPUTS For applications not requiring the use of the crystal oscillator input, both XTAL_IN and XTAL_OUT can be left floating. Though not required, but for additional protection, a 1k resistor can be tied from XTAL_IN to ground. REF_CLK INPUT For applications not requiring the use of the reference clock, it can be left floating. Though not required, but for additional protection, a 1k resistor can be tied from the REF_CLK to ground. IDTTM / ICSTM LVHSTL FREQUENCY SYNTHESIZER 8 ICS8422002AGI-01 REV. C NOVEMBER 1, 2007 ICS8422002I-01 FEMTOCLOCKSTM CRYSTAL-TO-LVHSTL FREQUENCY SYNTHESIZER PRELIMINARY Crystal Input Interface The ICS8422002I-01 has been characterized with 18pF parallel resonant crystals. The capacitor values shown in Figure 2 below were determined using a 25MHz 18pF parallel resonant crystal and were chosen to minimize the ppm error. XTAL_IN C1 22p X1 18pF Parallel Crystal XTAL_OUT C2 22p Figure 2. Crystal Input Interface LVCMOS to XTAL Interface The XTAL_IN input can accept a single-ended LVCMOS signal through an AC coupling capacitor. A general interface diagram is shown in Figure 3. The XTAL_OUT pin can be left floating. The input edge rate can be as slow as 10ns. For LVCMOS inputs, it is recommended that the amplitude be reduced from full swing to half swing in order to prevent signal interference with the power rail and to reduce noise. This configuration requires that the output impedance of the driver (Ro) plus the series resistance (Rs) equals the transmission line impedance. In addition, matched termination at the crystal input will attenuate the signal in half. This can be done in one of two ways. First, R1 and R2 in parallel should equal the transmission line impedance. For most 50 applications, R1 and R2 can be 100. This can also be accomplished by removing R1 and making R2 50. VDD VDD R1 Ro Rs 50 0.1f XTAL_IN Zo = Ro + Rs R2 XTAL_OUT Figure 3. General Diagram for LVCMOS Driver to XTAL Input Interface IDTTM / ICSTM LVHSTL FREQUENCY SYNTHESIZER 9 ICS8422002AGI-01 REV. C NOVEMBER 1, 2007 ICS8422002I-01 FEMTOCLOCKSTM CRYSTAL-TO-LVHSTL FREQUENCY SYNTHESIZER PRELIMINARY Schematic Example Figure 4 shows an example of ICS8422002I-01 application schematic. In this example, the device is operated at VDD = 3.3V. Both input options are shown. The device can either be driven using a quartz crystal or a 3.3V LVCMOS signal. The C1= 22pF and C2 = 22pF are recommended for frequency accuracy. For different board layout, the C1 and C2 may be slightly adjusted for optimizing frequency accuracy. The LVHSTL output driver termination examples are shown in this schematic. The decoupling capacitor should be located as close as possible to the power pin. Figure 4. ICS8422002I-01 Schematic Example IDTTM / ICSTM LVHSTL FREQUENCY SYNTHESIZER 10 ICS8422002AGI-01 REV. C NOVEMBER 1, 2007 ICS8422002I-01 FEMTOCLOCKSTM CRYSTAL-TO-LVHSTL FREQUENCY SYNTHESIZER PRELIMINARY Power Considerations This section provides information on power dissipation and junction temperature for the ICS8422002I-01. Equations and example calculations are also provided. 1. Power Dissipation. The total power dissipation for the ICS8422002I-01 is the sum of the core power plus the power dissipated in the load(s). The following is the power dissipation for VDD = 3.3V + 5% = 3.465V, which gives worst case results. NOTE: Please refer to Section 3 for details on calculating power dissipated in the load. * * Power (core)MAX = VDD_MAX * IDD_MAX = 3.465V * 100mA = 346.5mW Power (outputs)MAX = 32.8mW/Loaded Output pair If all outputs are loaded, the total power is 2 x 32.8mW = 65.6mW Total Power_MAX (3.465V, with all outputs switching) = 346.5mW + 65.6mW = 412.1mW 2. Junction Temperature. Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. The maximum recommended junction temperature for HiPerClockS devices is 125C. The equation for Tj is as follows: Tj = JA * Pd_total + TA Tj = Junction Temperature JA = Junction-to-Ambient Thermal Resistance Pd_total = Total Device Power Dissipation (example calculation is in section 1 above) TA = Ambient Temperature In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance JA must be used. Assuming a moderate air flow of 200 linear feet per minute and a multi-layer board, the appropriate value is 66.6C/W per Table 6 below. Therefore, Tj for an ambient temperature of 85C with all outputs switching is: 85C + 0.412W * 66.6C/W = 112.4C. This is well below the limit of 125C. This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type of board (single layer or multi-layer). Table 6. Thermal Resistance JA for 20 Lead TSSOP, Forced Convection JA by Velocity Linear Feet per Minute Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards 0 114.5C/W 73.2C/W 200 98.0C/W 66.6C/W 500 88.0C/W 63.5C/W IDTTM / ICSTM LVHSTL FREQUENCY SYNTHESIZER 11 ICS8422002AGI-01 REV. C NOVEMBER 1, 2007 ICS8422002I-01 FEMTOCLOCKSTM CRYSTAL-TO-LVHSTL FREQUENCY SYNTHESIZER PRELIMINARY 3. Calculations and Equations. The purpose of this section is to derive the power dissipated into the load. LVHSTL output driver circuit and termination are shown in Figure 5. VDDO Q1 VOUT RL 50 Figure 5. LVHSTL Driver Circuit and Termination To calculate worst case power dissipation into the load, use the following equations which assume a 50 load. Pd_H is power dissipation when the output drives high. Pd_L is the power dissipation when the output drives low. Pd_H = (VOH_MAX /RL) * (VDDO_MAX - VOH_MAX) Pd_L = (VOL_MAX /RL) * (VDDO_MAX - VOL_MAX) Pd_H = (1.0V/50) * (2V - 1.0V) = 20mW Pd_L = (0.4V/50) * (2V - 0.4V) = 12.8mW Total Power Dissipation per output pair = Pd_H + Pd_L = 32.8mW IDTTM / ICSTM LVHSTL FREQUENCY SYNTHESIZER 12 ICS8422002AGI-01 REV. C NOVEMBER 1, 2007 ICS8422002I-01 FEMTOCLOCKSTM CRYSTAL-TO-LVHSTL FREQUENCY SYNTHESIZER PRELIMINARY Reliability Information Table 7. JA vs. Air Flow Table for a 20 Lead TSSOP JA by Velocity Linear Feet per Minute Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards 0 114.5C/W 73.2C/W 200 98.0C/W 66.6C/W 500 88.0C/W 63.5C/W Transistor Count The transistor count for ICS8422002I-01 is: 2951 Package Outline and Package Dimension Package Outline - G Suffix for 20 Lead TSSOP Table 8. Package Dimensions All Dimensions in Millimeters Symbol Minimum Maximum N 20 A 1.20 A1 0.05 0.15 A2 0.80 1.05 b 0.19 0.30 c 0.09 0.20 D 6.40 6.60 E 6.40 Basic E1 4.30 4.50 e 0.65 Basic L 0.45 0.75 0 8 aaa 0.10 Reference Document: JEDEC Publication 95, MO-153 IDTTM / ICSTM LVHSTL FREQUENCY SYNTHESIZER 13 ICS8422002AGI-01 REV. C NOVEMBER 1, 2007 ICS8422002I-01 FEMTOCLOCKSTM CRYSTAL-TO-LVHSTL FREQUENCY SYNTHESIZER PRELIMINARY Ordering Information Table 9. Ordering Information Part/Order Number 8422002AGI-01 8422002AGI-01T 8422002AGI-01LF 8422002AGI-01LFT Marking ICS22002AI01 ICS22002AI01 TBD TBD Package 20 Lead TSSOP 20 Lead TSSOP "Lead-Free" 20 Lead TSSOP "Lead-Free" 20 Lead TSSOP Shipping Packaging Tube 2500 Tape & Reel Tube 2500 Tape & Reel Temperature -40C to 85C -40C to 85C -40C to 85C -40C to 85C NOTE: Parts that are ordered with an "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant. While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology (IDT) assumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial and industrial applications. Any other applications, such as those requiring high reliability or other extraordinary environmental requirements are not recommended without additional processing by IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT product for use in life support devices or critical medical instruments. IDTTM / ICSTM LVHSTL FREQUENCY SYNTHESIZER 14 ICS8422002AGI-01 REV. C NOVEMBER 1, 2007 ICS8422002I-01 FEMTOCLOCKSTM CRYSTAL-TO-LVHSTL FREQUENCY SYNTHESIZER PRELIMINARY Innovate with IDT and accelerate your future networks. Contact: www.IDT.com For Sales 800-345-7015 408-284-8200 Fax: 408-284-2775 For Tech Support netcom@idt.com 480-763-2056 Corporate Headquarters Integrated Device Technology, Inc. 6024 Silver Creek Valley Road San Jose, CA 95138 United States 800 345 7015 +408 284 8200 (outside U.S.) Asia Pacific and Japan Integrated Device Technology Singapore (1997) Pte. Ltd. Reg. No. 199707558G 435 Orchard Road #20-03 Wisma Atria Singapore 238877 +65 6 887 5505 Europe IDT Europe, Limited 321 Kingston Road Leatherhead, Surrey KT22 7TU England +44 (0) 1372 363 339 Fax: +44 (0) 1372 378851 www.IDT.com (c) 2007 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT and the IDT logo are trademarks of Integrated Device Technology, Inc. Accelerated Thinking is a service mark of Integrated Device Technology, Inc. All other brands, product names and marks are or may be trademarks or registered trademarks used to identify products or services of their respective owners. Printed in USA |
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